This description relates to integrated circuit metrology.
Metrology involves the measurement of silicon wafers, for example, in three different modes of operation: in-line operation in which wafer measurements are performed between process steps, in-situ operation in which the wafer is measured during processing, and off-line operation in which the wafer is removed from the process line for measurement. Metrology is an important operation in the introduction of new materials, processes, and structures associated with reduction of integrated circuit feature sizes. Metrology is also important for improving yield in mature fabrication lines. Through better characterization of variation due to process tools and processes, metrology can be used to reduce time-to-market and cost-of-manufacturing.
Measurements are often performed during the processing of an integrated circuit to gauge whether a process or process flow will result in the intended integrated circuit. The term metrology refers to the tools that make physical measurements on test and production wafers as well as the strategies for determining where on the wafer or die those measurements are to be taken. Measurement strategies may include measuring a particular group of sites on a die or across the wafer in a particular pattern or on particular structure within the die. Performing the measurements between process steps allows for easier isolation of a problem to a particular step and feature versus measuring the final circuit and then trying to diagnose which of 20 or 30 process steps caused the problem.
In determining which sites or locations to measure within a particular chip or die and which die to measure from among the multiple dies across the wafer, several factors come into play. Making too many measurements delays subsequent processing of the wafer, thus directly affecting manufacturing throughput and process yield. Making too many measurements may also produce too large a volume of raw data for a process engineer or diagnostic system to analyze in real-time.
As shown in FIG. 1A, test structures or devices 25 are sometimes created on the wafer outside the circuitry of the chip, normally in scribe or kerf lines 23, and the metrology is focused on those test structures or devices. The isolated test structure 25 may not resemble the features 29 in the IC design 24 that entail a problematic variation.
If pattern dependencies, such as density, linewidth, and linespace cause variation in electrical performance, a feature and its surrounding features may need to be measured. Interactions between vertical layers may also need to be considered. These considerations may grow in importance as different types of circuitry are consolidated densely onto a single chip, for example, in a mixed mode system-on-a-chip (SOC) design 24 in which analog, logic, I/O, and RAM components are designed into one chip.